The present invention relates, in general, to integrated circuits and, more particularly, to phase-frequency detector circuits.
Phase-locked loops (PLLS) are widely used for clock generation in data communication systems, local area networks, data storage applications, disc drives, and microprocessors. The five parts of a phase-locked loop typically include a phase-frequency detector (PFD), a charge-pump, a low-pass loop filter, a voltage-controlled oscillator (VCO), and a programmable divider. The PLL minimizes the skews of the phase and the frequency between an externally supplied reference clock and a feedback signal that is generated by the VCO and transferred to the programmable divider.
The PFD monitors the relative timing between the edges of the reference clock and the feedback signal and generates two output pulses of varying width that indicate whether the reference clock leads or lags the feedback signal. The output pulses are used for adjusting an analog signal that controls the VCO operating frequency, thus minimizing the skews of the phase and the frequency between the reference clock and the feedback signal from the programmable divider.
The phase offset and maximum frequency of the PLL system can be limited by the linearity and frequency response of the PFD. Typically, the PFD uses latches to detect the phase-frequency relationship between the reference clock and the feedback signal. The latches switch states at the transition edges of the reference clock and the feedback signal. A comparison of the outputs of the latches determines both the width of the pulses that are generated at the output of the PFD and the phase relationship between the reference clock and the feedback signals, i.e., whether the feedback signal leads or lags the reference clock. After the comparison of the latched output signals, the latches are switched to a state that allows detection of the next transition of the reference clock and the feedback signal edges. The maximum frequency of the PFD is limited by the speed of the circuitry that switches the latches to the state that allows detection of the next edges of the reference clock and the feedback signal.
Accordingly, it would be advantageous to have a circuit that increases the operating frequency of the phase-frequency detector.